Workshops
Publications
- Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation, D. Nikolos, H. T. Vergos & P. Mitsiadis, 1st IEEE International On - Line Testing Workshop, July 4-6, 1995, Nice, France.
- On The Testability Of Low - Power Optimized Circuits, M. Perakis, H. T. Vergos & D. Nikolos, 2nd IEEE International On - Line Testing Workshop Biarritz, France, July 8-10, 1996, pp. 154-157.
- On - Line Path Delay Fault Testing of Omega MINs, M. Bellos, E. Kalligeros, D. Nikolos & H. T. Vergos, 5th IEEE International On - Line Testing Workshop, July 5-7, 1999, Rhodes, Greece, pp. 133 - 137.
- A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme, H. T. Vergos, D. Nikolos, M. Bellos & C. Efstathiou, 2nd IEEE Latin American Testing Workshop (LATW 2001), February 11-14, 2001, Cancun, Mexico, pp. 242 - 247.
- KoVer : A Sophisticated Residue Arithmetic Core Generator, N. Kostaras & H. T. Vergos, 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), June 8-10, Montreal, Canada, pp.261-264.