H. T. Vergos - Professor

Workshop Publications

• D. Nikolos, H. T. Vergos and P. Mitsiadis, Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation, 1^st IEEE International On-Line Testing Workshop, July 4-6, 1995, Nice, France.

• M. Perakis, H. T. Vergos and D. Nikolos, On The Testability Of Low-Power Optimized Circuits, 2^nd IEEE International On-Line Testing Workshop Biarritz, France, July 8-10, 1996, pp. 154-157.

• M. Bellos, E. Kalligeros, D. Nikolos and H. T. Vergos, On-Line Path Delay Fault Testing of Omega MINs, 5^th IEEE International On-Line Testing Workshop, July 5-7, 1999, Rhodes, Greece, pp. 133-137.

• H. T. Vergos, D. Nikolos, M. Bellos and C. Efstathiou, A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme, 2^nd IEEE Latin American Testing Workshop (LATW 2001), February 11-14, 2001, Cancun, Mexico, pp. 242 - 247.

• N. Kostaras and H. T. Vergos, KoVer: A Sophisticated Residue Arithmetic Core Generator, 16^th IEEE International Workshop on Rapid System Prototyping (RSP 2005), June 8-10, Montreal, Canada, pp.261-264.