Publications
Fault Tolerant Cache Memory Design, H. T. Vergos, Department of Computer Engineering and Informatics, University of Patras, Greece, February 1996.
Abstract : Single chip VLSI processors use on-chip cache memories to satisfy the increasing memory bandwidth demands and offer reduced latency to the CPU. The area that these on-chip caches occupy is already a large fraction of the total chip area and is expected to increase further in the near future. Due to their area, a large portion of the manufacturing defects of the chip are expected to appear at the cache memories. By tolerating the resulting faults the yield of VLSI processor chips can be enhanced considerably. It has been shown, that the performance degradation imposed by the already proposed, in the open literature, techniques may be considerable and in some cases intolerable. To this aim, three novel fault tolerance techniques for on-chip cache memories are presented in this dissertation that can both enhance the yield considerably and offer significantly smaller performance degradation than the already known techniques.