H. T. Vergos - Professor

Journal Publications

• H. T. Vergos and D. Nikolos, Efficient Fault Tolerant Cache Memory Design, Microprocessing and Microprogramming - The Euromicro Journal, Vol. 41, 1995, pp. 153-169.

• D. Nikolos and H. T. Vergos, On the Yield of VLSI Processors with On Chip CPU Cache, IEEE Transactions on Computers, Vol. 48, No 10, October 1999, pp. 1138-1144.

• L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos and J. Kalamatianos, High-Speed Parallel-Prefix Modulo 2ⁿ-1 Adders, IEEE Transactions on Computers, Special Issue on Computer Arithmetic, Vol. 49, No 7, July 2000, pp. 673-680.

• H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, Path Delay Fault Testing of Multiplexer-Based Shifters, International Journal of Electronics, Vol. 88, No. 8, August 2001, pp. 923-937.

• D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos and G. Ph. Alexiou, Low Power Built-In Self-Test Schemes for Array and Booth Multipliers, VLSI Design, Vol. 12, No. 3, August 2001, pp. 431-448.

• D. Bakalis, Em. Kalligeros, D. Nikolos, H. T. Vergos and G. Ph. Alexiou, On the Design of Low Power BIST for Multipliers with Booth Encoding and Wallace Tree Summation, Journal of Systems Architecture, Vol. 48, No. 4-5, December 2002, pp. 125-135.

• H. T. Vergos, C. Efstathiou and D. Nikolos, Diminished-One Modulo 2ⁿ+1 Adder Design, IEEE Transactions on Computers, Vol. 51, No. 12, December 2002, pp. 1389-1399.

• C. Efstathiou, H. T. Vergos and D. Nikolos, Handling Zero in Diminished-One Modulo 2ⁿ+1 Adders, International Journal of Electronics, Vol. 90, No. 2, February 2003, pp. 133-144.

• H. T. Vergos, D. Nikolos, M. Bellos and C. Efstathiou, Deterministic BIST for RNS Adders, IEEE Transactions on Computers, Vol. 52, No. 7, July 2003, pp. 896-906.

• C. Efstathiou, H. T. Vergos and D. Nikolos, Modulo 2ⁿ±1 Adder Design Using Select-Prefix Blocks, IEEE Transactions on Computers, Vol. 52, No. 11, November 2003, pp. 1399-1406.

• C. Efstathiou, H. T. Vergos and D. Nikolos, Modified Booth Modulo 2ⁿ-1 Multipliers, IEEE Transactions on Computers, Vol. 53, No. 3, March 2004, pp. 370-374.

• C. Efstathiou, H. T. Vergos and D. Nikolos, Fast Parallel-Prefix Modulo 2ⁿ+1 Adders, IEEE Transactions on Computers, Vol. 53, No.9, September 2004, pp. 1211-1216.

• C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos and D. Nikolos, Efficient Diminished-1 Modulo 2ⁿ+1 Multipliers, IEEE Transactions on Computers, Vol. 54, No. 4, April 2005, pp. 491-496.

• H. T. Vergos and C. Efstathiou, Diminished-1 Modulo 2ⁿ+1 Squarer Design, IEE Proceedings - Computers and Digital Techniques, Vol. 152, No. 5, September 2005, pp. 561-566.

• H. T. Vergos and C. Efstathiou, On the Design of Efficient Modular Adders, Journal of Circuits, Systems and Computers, Vol. 14, No. 5, October 2005, pp. 965-972.

• D. Bakalis, M. Bellos, K. Adaos, D. Lymperopoulos, H. T. Vergos, G. Alexiou and D. Nikolos, A Core Generator for Arithmetic Cores and Testing Structures with a Network Interface, Journal of Systems Architecture, Vol. 52, No. 1, January 2006, pp. 1-12.

• D. Adamidis and H. T. Vergos, RNS Multiplication / Sum-of-Squares Units, IET Computers and Digital Techniques, Vol. 1, No. 1, January 2007, pp. 38-48.

• H. T. Vergos and C. Efstathiou, Design of Efficient Modulo 2ⁿ+1 Multipliers, IET Computers and Digital Techniques, Vol. 1, No. 1, January 2007, pp. 49-57.

• H. T. Vergos and C. Efstathiou, A Unifying Approach for Weighted and Diminished-1 Modulo 2ⁿ+1 Addition, IEEE Transactions on Circuits and Systems – II, Vol. 55, No. 10, October 2008, pp. 1041–1045.

• D. Bakalis and H. T. Vergos, Shifter Circuits for {2ⁿ+1, 2ⁿ, 2ⁿ-1} RNS, IET Electronics Letters, Vol. 45, No. 1, 1st January 2009, pp. 27-29.

• H. T. Vergos and C. Efstathiou, Efficient Modulo 2ⁿ+1 Adder Architectures, Integration, the VLSI Journal, Vol. 42, No. 2, February 2009, pp. 149–157.

• H. T. Vergos, D. Bakalis and C. Efstathiou, Fast Modulo 2ⁿ+1 Multi-Operand Adders and Residue Generators, Integration, the VLSI Journal, Vol. 43, No. 1, January 2010, pp. 42–48.

• H. T. Vergos and D. Bakalis, On Implementing Efficient Modulo 2ⁿ+1 Arithmetic Components, Journal of Circuits, Systems and Computers, Vol. 19, No. 5, August 2010, pp. 911-930.

• D. Bakalis, H. T. Vergos and A. Spyrou, Efficient Modulo 2ⁿ±1 Squarers, Integration, the VLSI Journal, Vol. 44, No. 3, June 2011, pp. 163-174.

• E. Vassalos, D. Bakalis and H. T. Vergos, On the Design of Modulo 2ⁿ±1 Subtractors and Adders/Subtractors, Circuits, Systems and Signal Processing, Vol. 30, No. 6, December 2011, pp. 1445-1461.

• H. T. Vergos and G. Dimitrakopoulos, On Modulo 2ⁿ+1 Adder Design, IEEE Transactions on Computers, Vol. 61, No. 2, February 2012, pp. 173-186.

• H. T. Vergos and D. Bakalis, Area-Time Efficient Multi-Modulus Adders and their Applications, Microprocessors and Microsystems - Embedded Hardware Design, Vol. 36, No. 5, July 2012, pp. 409–419.

• H. T. Vergos, Area-Time Efficient End-Around Inverted Carry Adders, Integration, the VLSI Journal, Vol. 45, No. 4, September 2012, pp. 388–394.

• H. T. Vergos, D. Bakalis and A. Anastasiou, Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators, Circuits, Systems and Signal Processing, Vol. 34, No. 4, April 2015, pp. 1041-1056.