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Journals

Publications

  • Efficient Fault Tolerant Cache Memory Design, H. T. Vergos and D. Nikolos, Microprocessing and Microprogramming - The Euromicro Journal, Vol. 41, 1995, pp. 153-169.


  • On the yield of VLSI Processors with On Chip CPU Cache, D. Nikolos and H. T. Vergos, IEEE Transactions on Computers, Vol. 48, No 10, October 1999, pp. 1138-1144.


  • High-Speed Parallel-Prefix Modulo 2n-1 Adders, L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos and J. Kalamatianos, IEEE Transactions on Computers, Special Issue on Computer Arithmetic, Vol. 49, No 7, July 2000, pp. 673-680.


  • Path Delay Fault Testing of Multiplexer-Based Shifters, H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, International Journal of Electronics, Vol. 88, No. 8, August 2001, pp. 923-937.


  • Low Power Built-In Self-Test Schemes for Array and Booth Multipliers, D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos and G. Ph. Alexiou, VLSI Design, Vol. 12, No. 3, August 2001, pp. 431-448.


  • On the Design of Low Power BIST for Multipliers with Booth Encoding and Wallace Tree Summation, D. Bakalis, Em. Kalligeros, D. Nikolos, H. T. Vergos and G. Ph. Alexiou, Journal of Systems Architecture, Vol. 48, No. 4-5, December 2002, pp. 125-135.


  • Diminished-One Modulo 2n+1 Adder Design, H. T. Vergos, C. Efstathiou and D. Nikolos, IEEE Transactions on Computers, Vol. 51, No. 12, December 2002, pp. 1389-1399.


  • Handling Zero in Diminished-One Modulo 2n+1 Adders, C. Efstathiou, H. T. Vergos and D. Nikolos, International Journal of Electronics, Vol. 90, No. 2, February 2003, pp. 133-144.


  • Deterministic BIST for RNS Adders, H. T. Vergos, D. Nikolos, M. Bellos and C. Efstathiou, IEEE Transactions on Computers, Vol. 52, No. 7, July 2003, pp. 896-906.


  • Modulo 2n±1 Adder Design Using Select-Prefix Blocks, C. Efstathiou, H. T. Vergos and D. Nikolos, IEEE Transactions on Computers, Vol. 52, No. 11, November 2003, pp. 1399-1406.


  • Modified Booth Modulo 2n-1 Multipliers, C. Efstathiou, H. T. Vergos and D. Nikolos, IEEE Transactions on Computers, Vol. 53, No. 3, March 2004, pp. 370-374.


  • Fast Parallel-Prefix Modulo 2n+1 Adders,C. Efstathiou, H. T. Vergos and D. Nikolos, IEEE Transactions on Computers, Vol. 53, No.9, September 2004, pp. 1211-1216.


  • Efficient Diminished-1 Modulo 2n+1 Multipliers, C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos and D. Nikolos, IEEE Transactions on Computers, Vol. 54, No. 4, April 2005, pp. 491-496.


  • Diminished-1 Modulo 2n+1 Squarer Design, H. T. Vergos and C. Efstathiou, IEE Proceedings - Computers and Digital Techniques, Vol. 152, No. 5, September 2005, pp. 561-566.


  • On the Design of Efficient Modular Adders, H. T. Vergos and C. Efstathiou, Journal of Circuits, Systems and Computers, Vol. 14, No. 5, October 2005, pp. 965-972.


  • A Core Generator for Arithmetic Cores and Testing Structures with a Network Interface, D. Bakalis, M. Bellos, K. Adaos, D. Lymperopoulos, H. T. Vergos, G. Alexiou and D. Nikolos, Journal of Systems Architecture, Vol. 52, No. 1, January 2006, pp. 1-12.


  • RNS Multiplication / Sum-of-Squares Units, D. Adamidis and H. T. Vergos, IET Computers and Digital Techniques, Vol. 1, No. 1, January 2007, pp. 38-48.


  • Design of Efficient Modulo 2n+1 Multipliers, H. T. Vergos and C. Efstathiou, IET Computers and Digital Techniques, Vol. 1, No. 1, January 2007, pp. 49-57.


  • A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition, H. T. Vergos and C. Efstathiou, IEEE Transactions on Circuits and Systems – II, Vol. 55, No. 10, October 2008, pp. 1041–1045.


  • Shifter Circuits for {2n+1, 2n, 2n-1} RNS, D. Bakalis and H. T. Vergos, IET Electronics Letters, Vol. 45, No. 1, 1st January 2009, pp. 27-29.


  • Efficient Modulo 2n+1 Adder Architectures, H. T. Vergos and C. Efstathiou, Integration, the VLSI Journal, Vol. 42, No. 2, February 2009, pp. 149–157.


  • Fast Modulo 2n+1 Multi-Operand Adders and Residue Generators, H. T. Vergos, D. Bakalis and C. Efstathiou, Integration, the VLSI Journal, Vol. 43, No. 1, January 2010, pp. 42–48.

  • On Implementing Efficient Modulo 2n+1 Arithmetic Components , H. T. Vergos and D. Bakalis, Journal of Circuits, Systems, and Computers, Vol. 19, No. 5, August 2010, to appear.

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