H. T. Vergos - Professor

H. T. Vergos received the Computer Engineering Diploma and the Ph.D. degree for his research on fault tolerant cache memory architectures, from the Computer Engineering and Informatics Department (CEID), University of Patras, in 1991 and 1996, respectively.

He then worked as an ASIC designer for Atmel Inc. He was a member of the team that developed the first worldwide IEEE 802.11 compliant medium access control processor and other network components. He rejoined CEID as a faculty member in 1998 and has since elevated up to a full Professor position.

His research focuses on arithmetic circuit architectures, VLSI design and test, rapid prototyping of computer systems using programmable logic and graceful degradation for fault tolerance, having more than 100 total publications in these fields. He serves as a reviewer in all well-known conferences and accredited journals in these fields and he is a senior IEEE Member.

He teaches the undergraduate courses "Introduction to Computer Systems" and "E-CAD for Digital Hardware" as well as the "Fault Tolerant Computer Systems" graduate course. In the past he taught several other courses and supervised a number of laboratories. He also supervised the development and test of AT91, a complete platform for the undergraduate lab courses of CEID.

He is the Director of the Hardware Technology and Computer Architecture Lab. He was the Head of the Hardware and Computer Architecture Division in 2008-2009, in 2014-2015 and in 2023-2024, as well as, the Director of the Laboratory for Computing (Computer Center) of CEID in 2011-2012 and 2013-2014 and the Director of the Microelectronics Lab in 2022-2025.

 

 

 

 

 

 

 

 

 

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