H. T. Vergos' Homepage

• Fault Tolerant CPU Cache Memory Design, H. T. Vergos & D. Nikolos, Computer Technology Institute Technical Report No 94.12.59, Patras, Greece, December 1994.

• Performance Recovery in Faulty Direct-Mapped Caches via the Use of a Very Small Fully Associative Spare Cache, H. T. Vergos & D. Nikolos, Computer Technology Institute Technical Report No 94.12.60, Patras, Greece, December 1994.

• Reconfigurable CPU Cache Memory Design : Fault Tolerance and Performance Evaluation, H. T. Vergos, D. Nikolos & P. Mitsiadis, Computer Technology Institute Technical Report No 95.1.5, Patras, Greece, January 1995.

• On the Yield of VLSI Processors with on-chip CPU cache, D. Nikolos & H. T. Vergos, Computer Technology Institute Technical Report No 95.12.42, Patras, Greece, December 1995.

• Path Delay Fault Testable Modified Booth Multipliers, E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas & Th. Haniotakis, Computer Technology Institute Technical Report No 99.07.01, Patras, Greece, July 1999.

• Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers, G. Sidiropoulos, H. T. Vergos & D. Nikolos, Computer Technology Institute Technical Report No 99.07.05, Patras, Greece, July 1999.

• Low Power BIST for Wallace-Tree Based Fast Multipliers, D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos & G. Alexiou, Computer Technology Institute Technical Report No 99.09.07, Patras, Greece, September 1999.

• Modified Booth 1's Complement and Modulo 2ⁿ-1 Multipliers, C. Efstathiou & H. T. Vergos, Computer Technology Institute Technical Report No 2000.09.03, Patras, Greece, September 2000.

• Diminished-1 Modulo 2ⁿ+1 Adder Design, H. T. Vergos C. Efstathiou & D. Nikolos, Computer Technology Institute Technical Report No 2001.02.02, Patras, Greece, February 2001.

(All reports are made available by the Computer Technology's Institute R&D Secretary on demand )