H. T. Vergos - Professor

Technical Reports

• H. T. Vergos and D. Nikolos, Fault Tolerant CPU Cache Memory Design, Computer Technology Institute Technical Report No 94.12.59, Patras, Greece, December 1994.

• H. T. Vergos and D. Nikolos, Performance Recovery in Faulty Direct-Mapped Caches via the Use of a Very Small Fully Associative Spare Cache, Computer Technology Institute Technical Report No 94.12.60, Patras, Greece, December 1994.

• H. T. Vergos, D. Nikolos and P. Mitsiadis, Reconfigurable CPU Cache Memory Design : Fault Tolerance and Performance Evaluation, Computer Technology Institute Technical Report No 95.1.5, Patras, Greece, January 1995.

• D. Nikolos and H. T. Vergos, On the Yield of VLSI Processors with On-chip CPU Cache, Computer Technology Institute Technical Report No 95.12.42, Patras, Greece, December 1995.

• E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas and Th. Haniotakis, Path Delay Fault Testable Modified Booth Multipliers, Computer Technology Institute Technical Report No 99.07.01, Patras, Greece, July 1999.

• G. Sidiropoulos, H. T. Vergos and D. Nikolos, Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers, Computer Technology Institute Technical Report No 99.07.05, Patras, Greece, July 1999.

• D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Alexiou, Low Power BIST for Wallace-Tree Based Fast Multipliers, Computer Technology Institute Technical Report No 99.09.07, Patras, Greece, September 1999.

• C. Efstathiou and H. T. Vergos, Modified Booth 1's Complement and Modulo 2ⁿ-1 Multipliers, Computer Technology Institute Technical Report No 2000.09.03, Patras, Greece, September 2000.

• H. T. Vergos C. Efstathiou and D. Nikolos, Diminished-1 Modulo 2ⁿ+1 Adder Design, Computer Technology Institute Technical Report No 2001.02.02, Patras, Greece, February 2001.

(All reports can be made available by contacting the Computer Technology's Institute R&D Secretary)