H. T. Vergos' Homepage

• Performance Recovery in Direct-Mapped Faulty Caches via the Use of a Very Small Fully Associative Spare Cache, H. T. Vergos and D. Nikolos, IEEE International Computer Performance and Dependability Symposium (IPDS '95), Erlangen, Germany, April 24-26, 1995, pp. 326-332.

• Yield - Performance tradeoffs for VLSI processors with partially good two level caches, D. Nikolos, H. T. Vergos, A. Vazaios and S. Voulgaris, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '96), Boston, MA, USA, November 6-8, 1996, pp. 53-57.

• On Path Delay Fault Testing of Multiplexer - Based Shifters, H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, 9^th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March 4-6, 1999, pp. 20-23.

• Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks, D. Nikolos, Th. Haniotakis, H. T. Vergos and Y. Tsiatouhas, Design, Automation and Test in Europe Conference and Exhibition (DATE '99), Munich, Germany, March 9-12, 1999, pp. 112-116.

• Path Delay Fault Testing of Benes Multistage Interconnection Networks, H. T. Vergos, M Bellos and D. Nikolos, 6^th IEEE International Conference on Electronics, Circuits and Systems (ICECS '99), Pafos Cyprus, September 5-8, 1999, Volume II, pp. 1097 - 1100.

• Easily Testable Carry-Save Multipliers with respect to Path Delay Faults, Th. Haniotakis, H. T. Vergos, Y. Tsiatouhas, D. Nikolos and M. Nicolaidis, 2^nd Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8 1999, pp. 13-16.

• Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers, G. Sidiropoulos, H. T. Vergos and D. Nikolos, 8^th Asian Test Symposium (ATS '99), Shanghai, China, November 16 -18 1999, pp. 47-52.

• Path Delay Fault Testable Modified Booth Multipliers, E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas and Th. Haniotakis, XIV Design of Circuits and Integrated Systems Conference (DCIS '99), Palma de Mallorca, Spain, November 16-19 1999, pp. 301-306.

• Low power dissipation in BIST schemes for modified Booth multipliers, D. Bakalis, H. T. Vergos, D. Nikolos, X. Kavousianos and G. Ph. Alexiou, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'99), Albuquerque, New Mexico, USA, November 1-3, 1999, pp. 121-129.

• A Class of Easily Testable Path Delay Fault Testable Circuits, T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas and H. T. Vergos, 2000 Southwest Symposium on Mixed - Signal Design (ISSMSD 2000), San Diego, California, USA, February 27-29 2000, pp. 165-170.

• Low Power BIST for Wallace-Tree based Fast Multipliers, D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Ph. Alexiou, 1^st IEEE International Symposium on Quality Electronic Design (ISQED 2000), San Jose, California, USA, March 20-22, 2000, pp. 433-438.

• Early Design Phase of a Surveillance System built around Digital Wireless Subnetworks, H. T. Vergos, Design Automation and Test in Europe (DATE 2000), Paris, France, March 27-30, 2000, pp. 133-137.

• A Macro Generator for Arithmetic Cores, D. Bakalis, M. Bellos, H. T. Vergos, D. Nikolos and G. Alexiou, XV Design of Circuits and Integrated Systems Conference (DCIS '2000), Montpelier, France, November 21-24, 2000, pp. 734-739.

• Modified Booth 1's Complement and Modulo 2ⁿ-1 Multipliers, C. Efstathiou and H. T. Vergos, 7th IEEE International Conference on Electronics, Circuits and Systems, (ICECS '2K), Beirut, Lebanon, December 17-20, 2000, Volume II, pp. 637-640.

• On Accumulator-based Bit-Serial Test Response Compaction Schemes, D. Bakalis, D. Nikolos, H. T. Vergos and X. Kavousianos, IEEE International Symposium on Quality Electronic Design (ISQED 2001), San Jose, California, USA, March 26-28, 2001, pp. 350-355.

• High Speed Parallel-Prefix Modulo 2ⁿ+1 Adders for Diminished-One Operands, H. T. Vergos, C. Efstathiou and D. Nikolos, 15thIEEE Symposium on Computer Arithmetic (ARITH-15), Vail, Colorado, June 11-13, 2001, pp. 211-217.

• A 200-MHz RNS Core, H. T. Vergos, European Conference on Circuit Theory and Design (ECCTD '01), "Circuit Paradigm in the 21^st Century", August 28 - 31, 2001, Espoo, Finland, Vol. II, pp. 249 - 252.

• On the Design of Modulo 2ⁿ±1 Adders, C. Efstathiou, H. T. Vergos and D. Nikolos, 8^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2001), Malta, September 2-5, 2001, Vol. I, pp. 517-520.

• Ling Adders in CMOS standard cell technologies, C. Efstathiou, H. T. Vergos and D. Nikolos, 9^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2002), Dubrovnik, Croatia, September 15-18, 2002, Vol. II, pp. 485-489.

• Fast Parallel-Prefix Modulo 2ⁿ+1 adders, H. T. Vergos, C. Efstathiou and D. Nikolos, XVII Conference on Design of Circuits and Integrated Systems (DCIS' 2002), Santander, Spain, November 19-22, 2002, pp. 65-70.

• A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo 2ⁿ-1 Adders, G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, Vol. V, pp. 225-228.

• Efficient BIST Schemes for RNS Datapaths, D. G. Nikolos, D. Nikolos H. T. Vergos and C. Efstathiou, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, Vol. V, pp. 573-576.

• A family of Parallel-Prefix Modulo 2ⁿ-1 Adders, G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, 2003 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 24-26, 2003, pp. 326-336.

• An Efficient BIST scheme for High-Speed Adders, D. G. Nikolos, D. Nikolos, H. T. Vergos and C. Efstathiou, 9^th IEEE International On-Line Tesing Symposium (IOLTS 2003), Kos, Greece, July 7-9, 2003, pp. 89-93.

• On the Efficiency of Parallel-Prefix Adders, H. T. Vergos, 16^th European Conference on Circuits Theory and Design, (ECCTD'03), Krakow, Poland, 1-4 September 2003, Vol. II, pp. 265-268.

• Efficient Modulo 2ⁿ+1 Tree Multipliers for Diminished-1 Operands, C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos and D. Nikolos, 10^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS'03), Sharjah, United Arab Emirates, December 14-17, 2003, Vol. III, pp. 200-203.

• Diminished-1 Modulo 2ⁿ+1 Squarer Design, H. T. Vergos and C. Efstathiou, Euromicro Symposium on Digital System Design (DSD '04), Rennes, France, August 31-September 3, 2004, pp. 380-386.

• Modulo 2ⁿ-1 Multiplication / Sum-of-Squares Units, D. Adamidis and H. T. Vergos, European Conference on Circuit Theory and Design 2005 (ECCTD 2005), August 29-September 2, 2005, Vol. II, pp. 143-146.

• New Architectures for Modulo 2ⁿ-1 Adders, G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos and C. Efstathiou, 12^th IEEE International Conference on Electronics, Circuits and Systems, Grammath, Tunisia, December 11-14, 2005.

• Novel Modulo 2ⁿ+1 Multipliers, H. T. Vergos and C. Efstathiou, 9^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30-September 1, 2006, pp. 561-566.

• Efficient Modulo 2^k+1 Squarers, H. T. Vergos and C. Efstathiou, XXI Conference on Design of Circuits and Integrated Systems (DCIS 2006), Barcelona, November 22-24, 2006.

• An Efficient BIST Scheme for Non-Restoring Array Dividers, H. T. Vergos, 10^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2007), August 29-31, 2007, Lubeck, Germany, pp. 664-667.

• Fast Modulo 2ⁿ+1 Adder Architectures, H. T. Vergos, XXII Conference on Design of Circuits and Integrated Systems, Sevilla, Spain, November 21-23, 2007, pp. 476–481.

• Efficient Modulo 2ⁿ+1 Multi-operand Adders, H. T. Vergos, D. Bakalis and C. Efstathiou, 15^th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, August 31 – September 3, 2008, pp. 694–697.

• On the Use of Diminished-1 Adders for Weighted Modulo 2ⁿ+1 Arithmetic Components, H. T. Vergos and D. Bakalis, 11^th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2008), Parma, Italy, September 3–5, 2008, pp. 752–759.

• Efficient Architectures for Modulo 2ⁿ-1 Squarers, A. Spyrou, D. Bakalis and H. T. Vergos, 16^th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.

• Novel Modulo 2ⁿ+1 Subtractors, E. Vassalos, D. Bakalis and H. T. Vergos, 16^th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.