H. T. Vergos - Professor


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Conferences / Symposia

Publications

Conferences / Symposia Publications













  • D. Bakalis, M. Bellos, H. T. Vergos, D. Nikolos and G. Alexiou, A Macro Generator for Arithmetic Cores, XV Design of Circuits and Integrated Systems Conference (DCIS '2000), Montpelier, France, November 21-24, 2000, pp. 734-739.





  • H. T. Vergos, A 200-MHz RNS Core, European Conference on Circuit Theory and Design (ECCTD '01), "Circuit Paradigm in the 21st Century", August 28 - 31, 2001, Espoo, Finland, Vol. II, pp. 249 - 252.


  • C. Efstathiou, H. T. Vergos and D. Nikolos, On the Design of Modulo 2n±1 Adders, 8th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2001), Malta, September 2-5, 2001, Vol. I, pp. 517-520.



  • H. T. Vergos, C. Efstathiou and D. Nikolos, Fast Parallel-Prefix Modulo 2n+1 adders, XVII Conference on Design of Circuits and Integrated Systems (DCIS' 2002), Santander, Spain, November 19-22, 2002, pp. 65-70.



  • D. G. Nikolos, D. Nikolos, H. T. Vergos and C. Efstathiou, Efficient BIST Schemes for RNS Datapaths, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, Vol. V, pp. 573-576.


  • G. Dimitrakopoulos, H. T. Vergos, D. Nikolos and C. Efstathiou, A Family of Parallel-Prefix Modulo 2n-1 Adders, 2003 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2003), The Hague, The Netherlands, June 24-26, 2003, pp. 326-336.







  • G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos and C. Efstathiou, New Architectures for Modulo 2n-1 Adders, 12th IEEE International Conference on Electronics, Circuits and Systems, Grammath, Tunisia, December 11-14, 2005.


  • H. T. Vergos and C. Efstathiou, Novel Modulo 2n+1 Multipliers, 9th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2006), Cavtat near Dubrovnik, Croatia, August 30-September 1, 2006, pp. 168-175.


  • H. T. Vergos and C. Efstathiou, Efficient Modulo 2k+1 Squarers, XXI Conference on Design of Circuits and Integrated Systems (DCIS 2006), Barcelona, November 22-24, 2006.




  • H. T. Vergos, D. Bakalis and C. Efstathiou, Efficient Modulo 2n+1 Multi-operand Adders, 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, August 31 – September 3, 2008, pp. 694–697.




  • E. Vassalos, D. Bakalis and H. T. Vergos, Novel Modulo 2n+1 Subtractors, 16th International Conference on Digital Signal Processing (DSP 2009), Santorini, Greece, July 5-7, 2009.










  • H. T. Vergos, O. Giannou and D. Bakalis, Squarers in QCA Nanotechnology, 12th IEEE International Conference on Nanotechnology (IEEE-NANO), Birmingham, UK, August 20–23, 2012, pp. 689–694.


  • E. Vassalos, D. Bakalis and H. T. Vergos, SUT-RNS Residue-to-Binary Converters Design, 15th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD 2012), Cesme, Turkey, September 5-8, 2012, pp. 65–72.





  • A. Bikos and H. T. Vergos, Easily Verified IP Watermarking, Design & Technology of Integrated Systems at Nanoscale Era (DTIS 2014), Santorini, Greece, May 6-8, 2014.

























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